Using VCS

Using VCS in CS310H

Before running VCS the tool environment file must be source. If you have not done this please go back to the environment setup page. Steps 1 through 5 may be done on in a telnet window from anywhere to any department linux machine. Steps 6 on require the user be seated at a departement linux machine.

Write verilog file. For the purposes of this tutorial you may use the following example:

module counter ( out, clk, reset ) ; input clk, reset; output [3:0] out; reg [3:0] out; wire [3:0] next; // This statement implements reset and increment assign next = reset ? 4'b0 : (out + 4'b1); // This implements the flip-flops always @ ( posedge clk ) begin out <= #1 next; end endmodule // counter

This code implements a simple four bit counter.You may also copy the file from here.

Write a test bench for the verilog file. Here is an example testbench file:

// This stuff just sets up the proper time scale and format for the
// simulation, for now do not modify.
`timescale 1ns/10ps
module timeunit;
   initial $timeformat(-9,1," ns",9);
endmodule


// Here is the testbench proper:
module counter_testbench ( ) ;

    // Test bench gets wires for all device under test (DUT) outputs:

   wire [3:0]        out;

   // Regs for all DUT inputs:
   reg               clk;
   reg               reset;


   counter dut (// (dut means device under test)
                // Outputs
                .out            (out[3:0]),
                // Inputs
                .reset          (reset),
                .clk            (clk));


  // Setup clk to automatically strobe with a period of 20.
   always #10 clk = ~clk;


   initial
     begin

        // First setup up to monitor all inputs and outputs
        $monitor ("time=%5d ns, clk=%b, reset=%b, out=%b", $time, clk, reset, out[3:0]);

        // First initialize all registers
        clk = 1'b0;             // what happens to clk if we don't
                                // set this?;
        reset = 1'b0;

        @(posedge clk);#1;      // this  says wait for rising edge
                                // of clk and one more tic (to prevent
                                // shoot through)

        reset = 1'b1;

        @(posedge clk);#1;

        reset = 1'b0;

        // Lets watch what happens after 7 cycles
        @(posedge clk);#1;
        @(posedge clk);#1;
        @(posedge clk);#1;
        @(posedge clk);#1;
        @(posedge clk);#1;
        @(posedge clk);#1;
        @(posedge clk);#1;


        // At this point we should have a 4'b0110 coming out out because
        // the counter should have counted for 7 cycles from 0
        if (out != 4'b0110) begin
           $display("ERROR 1: Out is not equal to 4'b0110");
           $finish;
        end


        // We got this far so all tests passed.
        $display("All tests completed sucessfully\n\n");

        $finish;
     end


   // This is to create a dump file for offline viewing.
   initial
     begin
        $dumpfile ("counter.dump");
        $dumpvars (0, counter_testbench);
     end // initial begin


endmodule // counter_testbench

The testbench instantiates the counter and assigns each of its inputs to a reg. A new thing here is the "always #10 clk = ~clk;" statement. The tells the simulator to set the new value of clk to the inverse of its current value every 10ns yielding a period of 20ns. The testbench clears the value in clk and reset. Reset is allowed to go high for one full cycle and then the counter is let loose for seven cycles. At the end of the seven cycles if the output is incorrect it will print an error message and quit. You may download a copy of the testbench from here.

In order to use the test bench we must use VCS to build an executable model of it. To do this first we must make a list of the files we are building. The list of files must be in a top down heirarchical order. In this case we will make a text file called "counter_filelist" which has the following contents:
```
counter_testbench.v
counter.v
  
```
You may download a copy of this file from here .

The next step is to compile the verilog with vcs. For this example issue the command below (shown in red):

pgratz@desk workingdir $ vcs -o counter -Mupdate -f counter_filelist Chronologic VCS (TM) Version X-2005.06-SP2 -- Thu Sep 14 11:59:11 2006 Copyright (c) 1991-2005 by Synopsys Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. Parsing design file 'counter_testbench.v' Parsing design file 'counter.v' Top Level Modules: timeunit counter_testbench TimeScale is 1 ns / 10 ps Starting vcs inline pass... 2 modules and 0 UDP read. recompiling module timeunit recompiling module counter_testbench Both modules done. if [ -x ../counter ]; then chmod -x ../counter; fi g++ -o ../counter 5NrI_d.o 5NrIB_d.o IV5q_1_d.o blOS_1_d.o SIM_l.o /projects/cad/sy nopsys/vcs/vcs-mx_vX-2005.06-SP2/redhat30/lib/libvirsim.a /projects/cad/synopsys/vc s/vcs-mx_vX-2005.06-SP2/redhat30/lib/libvcsnew.so /projects/cad/synopsys/vcs/vcs-mx _vX-2005.06-SP2/redhat30/lib/ctype-stubs_32.a -ldl -lc -lm -ldl ../counter up to date CPU time: .080 seconds to compile + 2.588 seconds to link

Now that the model has been built the next step is to execute it to find out if the tests written in the testbench pass or not:

pgratz@desk workingdir $ ./counter Chronologic VCS simulator copyright 1991-2005 Contains Synopsys proprietary information. Compiler version X-2005.06-SP2; Runtime version X-2005.06-SP2; Sep 14 12:23 2006 time= 0 ns, clk=0, reset=0, out=xxxx time= 10 ns, clk=1, reset=0, out=xxxx time= 11 ns, clk=1, reset=1, out=xxxx time= 20 ns, clk=0, reset=1, out=xxxx time= 30 ns, clk=1, reset=1, out=xxxx time= 31 ns, clk=1, reset=0, out=0000 time= 40 ns, clk=0, reset=0, out=0000 time= 50 ns, clk=1, reset=0, out=0000 time= 51 ns, clk=1, reset=0, out=0001 time= 60 ns, clk=0, reset=0, out=0001 time= 70 ns, clk=1, reset=0, out=0001 time= 71 ns, clk=1, reset=0, out=0010 time= 80 ns, clk=0, reset=0, out=0010 time= 90 ns, clk=1, reset=0, out=0010 time= 91 ns, clk=1, reset=0, out=0011 time= 100 ns, clk=0, reset=0, out=0011 time= 110 ns, clk=1, reset=0, out=0011 time= 111 ns, clk=1, reset=0, out=0100 time= 120 ns, clk=0, reset=0, out=0100 time= 130 ns, clk=1, reset=0, out=0100 time= 131 ns, clk=1, reset=0, out=0101 time= 140 ns, clk=0, reset=0, out=0101 time= 150 ns, clk=1, reset=0, out=0101 time= 151 ns, clk=1, reset=0, out=0110 time= 160 ns, clk=0, reset=0, out=0110 time= 170 ns, clk=1, reset=0, out=0110 All tests completed successfully $finish at simulation time 171.0 ns V C S S i m u l a t i o n R e p o r t Time: 171000 ps CPU Time: 0.040 seconds; Data structure size: 0.0Mb Thu Sep 14 12:23:44 2006

Looking at the output we can see that the clk is strobing every 20 ns. Also note that at the end of the test we see the "All tests completed sucessfully" so the simulation reached the final count value successfully

For more extensive analysis of the device under test it can be useful to visually see the signals and their transitions as in the previous tutorial. As an exersize use the previous tutorial's instructions to bring up the VirSim wave trace window and verify the signal values.

This concludes the tutorial on the use of VCS. More extensive documentation may be found on the main CAD page.

Modified by Paul Gratz, pgratz@cs.utexas.edu