If-then-elses of 4vecs following the SystemVerilog semantics for procedural conditional branches, i.e. if the test has any bit that is exactly 1 (not 0, Z, or X), we choose the then branch, else the else branch. (Non-monotonic semantics).
Function:
(defun 4vec-?! (test then else) (declare (xargs :guard (and (4vec-p test) (4vec-p then) (4vec-p else)))) (let ((__function__ '4vec-?!)) (declare (ignorable __function__)) (b* (((4vec test)) (pick-else (equal 0 (logand test.upper test.lower)))) (if pick-else (4vec-fix else) (4vec-fix then)))))
Theorem:
(defthm 4vec-p-of-4vec-?! (b* ((choices (4vec-?! test then else))) (4vec-p choices)) :rule-classes :rewrite)
Theorem:
(defthm 4vec-?!-of-4vec-fix-test (equal (4vec-?! (4vec-fix test) then else) (4vec-?! test then else)))
Theorem:
(defthm 4vec-?!-4vec-equiv-congruence-on-test (implies (4vec-equiv test test-equiv) (equal (4vec-?! test then else) (4vec-?! test-equiv then else))) :rule-classes :congruence)
Theorem:
(defthm 4vec-?!-of-4vec-fix-then (equal (4vec-?! test (4vec-fix then) else) (4vec-?! test then else)))
Theorem:
(defthm 4vec-?!-4vec-equiv-congruence-on-then (implies (4vec-equiv then then-equiv) (equal (4vec-?! test then else) (4vec-?! test then-equiv else))) :rule-classes :congruence)
Theorem:
(defthm 4vec-?!-of-4vec-fix-else (equal (4vec-?! test then (4vec-fix else)) (4vec-?! test then else)))
Theorem:
(defthm 4vec-?!-4vec-equiv-congruence-on-else (implies (4vec-equiv else else-equiv) (equal (4vec-?! test then else) (4vec-?! test then else-equiv))) :rule-classes :congruence)