# Wildelim

Elimination of wildcard equality operators, ==? and !=?.

See SystemVerilog 2012, Section 11.4.6 Wildcard Equality Operators.
In brief:

- a ==? b determines whether a equals b, except that X and Z values in b
act as wildcards.
- a !=? b determines whether a does not equal b, except that X and Z
values in b act as wildcards.

These operators produce 1-bit, self-determined results. If a and
b are of unequal bit lengths, they are extended in the same manner as for
the logical equality/inequality operators. The result is X if the a
operand contains any X or Z bit that is not being compared with a
wildcard in the b operand.

These operators are basically fine and sensible when b is a constant
integer literal like 4'b0101 or a weird integer like 4'b01xx.
However, in the more general case where b is some expression that is
computed at runtime, these operators are fundamentally broken because they do
not treat X bits within b as unknowns. This poses problems for
back-end tools like esim that expect operators to behave
monotonically.

VL attempts to support simple uses of ==? and !=?, i.e., when the
right-hand argument is a constant or weird integer literal. In this case, we
can compute the mask of bits that we care about, and then consider the equality
of the masked expressions.

Ordering notes. We expect that this transform should be run after sizing.
Typically you will want to run it after sizing but before, e.g., truncating or
splitting expressions.

### Subtopics

- Vl-design-wildelim
- Top-level wildelim transform.
- Vl-expr-wildelim
- Top-level wrapper for eliminating ==? and !=? from an
expression. Avoids reconsing when there are no ==? or !=?
operators.