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• Primitives

*vl-1-bit-delay-1*

Primitive assignment with delay.

The Verilog definition of this module is:

module VL_1_BIT_DELAY_1 (out, in) ;
  output out;
  input in;
  assign #1 out = in;
endmodule

VL takes this as a primitive. It is used by our delayredux transform to separate delays from assignment statements.

The corresponding esim primitive is ACL2::*esim-del*, but note that esim really has no notion of delays and this ends up being equivalent to an ordinary *vl-1-bit-assign*.

Definition: *vl-1-bit-delay-1*

(defconst *vl-1-bit-delay-1*
  (b* ((name "VL_1_BIT_DELAY_1")
       (atts '(("VL_PRIMITIVE") ("VL_HANDS_OFF")))
       ((mv out-expr
            out-port out-portdecl out-vardecl)
        (vl-primitive-mkport "out" :vl-output))
       ((mv in-expr in-port in-portdecl in-vardecl)
        (vl-primitive-mkport "in" :vl-input))
       (one (vl-make-index 1))
       (delay (make-vl-gatedelay :rise one
                                 :fall one
                                 :high one))
       (assign (make-vl-assign :lvalue out-expr
                               :expr in-expr
                               :delay delay
                               :loc *vl-fakeloc*)))
    (hons-copy
         (make-vl-module :name name
                         :origname name
                         :ports (list out-port in-port)
                         :portdecls (list out-portdecl in-portdecl)
                         :vardecls (list out-vardecl in-vardecl)
                         :assigns (list assign)
                         :minloc *vl-fakeloc*
                         :maxloc *vl-fakeloc*
                         :atts atts
                         :esim acl2::*esim-del*))))