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• Primitives

*vl-1-bit-t*

Primitive 1 (true) generator.

The Verilog definition of this module is:

module VL_1_BIT_T (out) ;
  output out;
  assign out = 1'b1;
endmodule

VL takes this as a primitive. BOZO this module is currently unused but we are going to start using it soon.

The corresponding esim primitive is ACL2::*esim-t*.

Definition: *vl-1-bit-t*

(defconst *vl-1-bit-t*
  (b* ((name "VL_1_BIT_T")
       (atts '(("VL_PRIMITIVE") ("VL_HANDS_OFF")))
       ((mv out-expr
            out-port out-portdecl out-vardecl)
        (vl-primitive-mkport "out" :vl-output))
       (out-assign (make-vl-assign :lvalue out-expr
                                   :expr |*sized-1'b1*|
                                   :loc *vl-fakeloc*)))
    (hons-copy (make-vl-module :name name
                               :origname name
                               :ports (list out-port)
                               :portdecls (list out-portdecl)
                               :vardecls (list out-vardecl)
                               :assigns (list out-assign)
                               :minloc *vl-fakeloc*
                               :maxloc *vl-fakeloc*
                               :atts atts
                               :esim acl2::*esim-t*))))