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• Parse-ports

Sv-non-ansi-portdecls

Parsing of SystemVerilog-2012 non-ANSI port declarations.

NOTE: the port declarations we now describe are permitted in grammar rules such as module_item, interface_item, and program_item. In other words, they're things that are permitted in non-ANSI contexts like

module foo (o, a, b);
    output o;             <---- this kind of stuff
    ...
endmodule

These aren't the same as for fancy ANSI port declarations like

module foo (output logic [2:0] o, ...)

The grammar rules are:

port_declaration ::= {attribute_instance} inout_declaration
                   | {attribute_instance} input_declaration
                   | {attribute_instance} output_declaration
                   | {attribute_instance} ref_declaration             // NEW, not yet supported
                   | {attribute_instance} interface_port_declaration  // NEW, not yet supported

The declarations we will currently try to support are:

inout_declaration ::= 'inout' net_port_type      list_of_port_identifiers

input_declaration ::= 'input' net_port_type      list_of_port_identifiers
                    | 'input' variable_port_type list_of_variable_identifiers

output_declaration ::= 'output' net_port_type      list_of_port_identifiers
                     | 'output' variable_port_type list_of_variable_port_identifiers

See parse-port-types for the port-type handling.

As for the three different kinds of lists of identifiers, they are all quite similar to one another, differing only in the kinds of dimensions that are allowed and in whether or not default values are permitted. Here are their definitions:

list_of_port_identifiers          ::= identifier {unpacked_dimension} { ',' identifier {unpacked_dimension} }
list_of_variable_identifiers      ::= identifier {variable_dimension} { ',' identifier {variable_dimension} }
list_of_variable_port_identifiers ::= identifier {variable_dimension} [ '=' expression ]
                                      { ',' identifier {variable_dimension} [ '=' expression ] }

However, we don't yet implement default values. Section 23.2.2.4 talks about default port values, and says they can only be specified for input ports. But the grammar only permits them for output ports. That seems like a bug with the standard. By omitting them, the above reduce to:

list_of_port_identifiers          ::= identifier {unpacked_dimension} {',' identifier {unpacked_dimension} }
list_of_variable_identifiers      ::= identifier {variable_dimension} {',' identifier {variable_dimension} }
list_of_variable_port_identifiers ::= identifier {variable_dimension} {',' identifier {variable_dimension} }

Subtopics

Vl-parse-port-declaration-noatts-2012

Matches the rest of any port_declaration, after the attributes.

Vl-parse-port-declaration-noatts

Matches port_declaration for Verilog-2005 or SystemVerilog-2012, except for the initial attributes. Used for port declarations within modules.

Vl-parse-list-of-port-identifiers

Approximation of list_of_port_identifiers, list_of_variable_identifiers, and list_of_variable_port_identifiers.

Vl-parsed-portdecl-head->complete-p

Determines if a parsed net_port_type or variable_port_type is "completely declared" and should therefore create a net.