Representation of gate types.
We represent Verilog's gate types with the keyword symbols recognized by (vl-gatetype-p x).
This is an ordinary defenum.
Function:
(defun vl-gatetype-p (x) (declare (xargs :guard t)) (or (eq x ':vl-cmos) (eq x ':vl-rcmos) (eq x ':vl-bufif0) (eq x ':vl-bufif1) (eq x ':vl-notif0) (eq x ':vl-notif1) (eq x ':vl-nmos) (eq x ':vl-pmos) (eq x ':vl-rnmos) (eq x ':vl-rpmos) (eq x ':vl-and) (eq x ':vl-nand) (eq x ':vl-or) (eq x ':vl-nor) (eq x ':vl-xor) (eq x ':vl-xnor) (eq x ':vl-buf) (eq x ':vl-not) (eq x ':vl-tranif0) (eq x ':vl-tranif1) (eq x ':vl-rtranif1) (eq x ':vl-rtranif0) (eq x ':vl-tran) (eq x ':vl-rtran) (eq x ':vl-pulldown) (eq x ':vl-pullup)))
Theorem: type-when-vl-gatetype-p
(defthm type-when-vl-gatetype-p (implies (vl-gatetype-p x) (if (symbolp x) (if (not (equal x 't)) (not (equal x 'nil)) 'nil) 'nil)) :rule-classes :compound-recognizer)