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• Make-implicit-wires

Vl-genblock-make-implicit-wires

Only for genblocks that definitely introduce their own scope, e.g., named begin/end blocks or generate loops. (Not for conditional generate blocks because scoping is trickier there.)

Signature

(vl-genblock-make-implicit-wires x st warnings) 
  → 
(mv warnings st new-x)

Arguments

x — Guard (vl-genblock-p x).

st — Guard (vl-implicitst-p st).

warnings — Guard (vl-warninglist-p warnings).

Returns

warnings — Type (vl-warninglist-p warnings).

st — Type (vl-implicitst-p st).

new-x — Updated version of the block, extended with declarations for any implicit wires as necessary.
    Type (vl-genblock-p new-x).

SystemVerilog-2012 Section 6.10: wires that are implicitly declared within a generate block are local to that generate block. So we attach the implicit declarations for everything within this block to this scope, without leaking them into the outer context.