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Make-implicit-wires

Vl-genblock-under-cond-make-implicit-wires

Only for genblocks that are found in conditional contexts, i.e., the then/else branches of if statements, or the bodies of case statements. (Scoping is tricky here).

Signature
(vl-genblock-under-cond-make-implicit-wires x st warnings) → (mv warnings st new-x)
Arguments: x — Guard (vl-genblock-p x).; st — Guard (vl-implicitst-p st).; warnings — Guard (vl-warninglist-p warnings).
Returns: warnings — Type (vl-warninglist-p warnings).; st — Type (vl-implicitst-p st).; new-x — Updated version of the block, extended with declarations for any implicit wires as necessary.
Type (vl-genblock-p new-x).

This is slightly tricky because of the condnest case. For background see SystemVerilog-2012 Section 27.5 and see vl-genblock.

We are careful here not to introduce new scopes when we go into condnest ifs. Note though that the only places we could introduce implicit wires are always in the leaves of the IF structure, and the leaves always have a block.