Representation of wire (net) types, i.e., resolution function.
Note that Verilog/SystemVerilog net types like
This is an ordinary defenum.
Function:
(defun vl-nettypename-p (x) (declare (xargs :guard t)) (or (eq x ':vl-wire) (eq x ':vl-tri) (eq x ':vl-supply0) (eq x ':vl-supply1) (eq x ':vl-triand) (eq x ':vl-trior) (eq x ':vl-tri0) (eq x ':vl-tri1) (eq x ':vl-trireg) (eq x ':vl-uwire) (eq x ':vl-wand) (eq x ':vl-wor)))
Theorem: type-when-vl-nettypename-p
(defthm type-when-vl-nettypename-p (implies (vl-nettypename-p x) (if (symbolp x) (if (not (equal x 't)) (not (equal x 'nil)) 'nil) 'nil)) :rule-classes :compound-recognizer)