Gatesplit
Split up gates with "extra" terminals.
Gate Splitting
This transformation is responsible for splitting up multi-input gates into
multiple one-input gates for buf and not, or two-input gates for
and, or, etc. It also deals with degenerate cases like single-input
and gates, which are not ruled out by the Verilog specification.
Ordering Notes. This transformation must be done after widths have
been computed, and after replicate-insts has been run to eliminate any
arrays. Replication is necessary for certain well-formedness checks on the
widths to succeed.
Unlike occforming, we lay down gates directly instead of introducing new
modules. It might be nicer to do it the other way and introduce modules
instead, since then the module instance could keep the same name as the gate.
On the other hand, the code to just introduce gates is simpler, and it would
probably suffice to just use good names or annotations to explain where the
gates come from.
Subtopics
- Vl-gatesplit-nand/nor/xnor
- Split up a multi-input nand or nor gate, if necessary.
- Vl-modulelist-gatesplit
- (vl-modulelist-gatesplit x) maps vl-module-gatesplit across a list.
- Vl-gatesplit-and/or/xor
- Split up a multi-input and, or, xor, or xnor
gate, if necessary.
- Vl-degenerate-gate-to-buf
- Replace a degenerate one-input logic gate with a buffer.
- Vl-gatesplit-buf/not
- Split up a multi-output buf or not gate, if necessary.
- Vl-make-temporary-wires
- Generate expressions and declarations for some fresh, one-bit wires.
- Vl-gateinst-gatesplit
- Main routine for splitting high-arity gate instances.
- Vl-gateinstlist-gatesplit
- Vl-module-gatesplit
- Vl-design-gatesplit
- Top-level gatesplit transform.
