Trunc
Eliminate implicit truncations in assignments
This transformation must occur after expression splitting has
already been applied. Recall that the split transformation brings
all assignments into one of the following forms:
- lvalue = atom
- lvalue = (op atom1 atom2 ... atomN)
Unfortunately, Verilog allows for implicit truncations during assignments,
so that the lvalue's width might be less than the operation's width. (The
other case is that the widths agree, since the lvalue plays a role in the
ctxsize computation, and so if the lvalue's width is larger than the
expression's, the expression will be expanded to match.
And so we now introduce a rewrite which corrects for this, and results in
assignments where the expressions always agree on the desired sizes. The basic
transformation is as follows. We are looking at the assignment lvalue =
expr. If lvalue is shorter than expr, we replace this assignment
with something like:
wire [expr.width-1:0] trunc_12345;
assign trunc_12345 = expr;
assign lvalue = trunc_12345[lvalue.width-1:0];
where trunc_12345 is a fresh variable name. All of the resulting
assignments are between lvalues and expressions that agree.
Subtopics
- Vl-modulelist-trunc
- (vl-modulelist-trunc x) maps vl-module-trunc across a list.
- Vl-make-chopped-id
- Generate the expression to truncate a wire.
- Vl-assign-trunc
- Make any implicit truncation in an assignment explicit.
- Vl-truncate-weirdint
- Special routine for truncating unsigned weirdint literals without
introducing temporary wires.
- Vl-truncate-constint
- Special routine for truncating ordinary, unsigned constant integers,
without introducing temporary wires.
- Vl-assignlist-trunc
- Vl-module-trunc
- Eliminate implicit truncations in assignments throughout a module.
- Vl-design-trunc
- Top-level trunc transform.
- Vl-assignlist-can-skip-trunc-p
- Vl-assign-can-skip-trunc-p
