Expr-slicing
Functions for slicing up expressions into bits or segments.
We say a Verilog expression x is sliceable when it may
be "easily" converted into a concatenation, say { bit_N, bit_N-1, ...,
bit0 }, where each bit_i is either a one-bit wide constant (i.e.,
1'b0, 1'b1, 1'bX, or 1'bZ), or is a bit-select from a plain
identifier (i.e., foo[3]).
Sliceable expressions are of interest because they can be easily partitioned
into lists of individual bits or broken into segments, without having to
introduce any temporary wires.
(vl-expr-sliceable-p x) recognizes the expressions we regard as
sliceble. For the atoms, we allow:
We do not currently consider real
numbers or strings to be sliceable,
but in principle we could add support for this. It doesn't make sense to
regard the other kinds of atoms (HID pieces, function names, and system
function names) as sliceable.
Beyond these atoms, we regard resolved bit- and part-selects from
identifiers as sliceable. It is pretty obvious that the indicies of a
part-select need to be resolved for easy partitioning. But even though we know
that foo[i] is only a single-bit wide, we also insist that bit selects be
resolved because this is useful in functions like vl-msb-bitslice-expr
which convert sliceable expressions into actual lists of bits, and also in
vl-assign-occform where we assume we can just use plain assignments on
any sliceable expressions.
We say that concatenations of sliceable arguments as sliceable, as are
replications of sliceable arguments with resolved multiplicities.
Other expressions aren't sliceable. This seems generally sensible, e.g.,
what are the bits of a + b? With enough context it would be possible to
slice up hierarchical identifiers, but we don't try to do this since it would
be quite a bit more complex.
Subtopics
- Vl-expr-sliceable-p
- (vl-expr-sliceable-p x) determines if the expression x is
sliceable.
- Vl-msb-bitslice-expr
- Explode a well-typed,
sliceable expression into a list
of MSB-ordered, single-bit expressions.
