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A transform for inlining basic modules.
This transform can be used to inline modules as long as they are very simple. The modules being inlined can't have always blocks, registers, and so forth; more specifically they must be accepted by vl-ok-to-inline-p.
WARNING: We assume that the modules involved are "sensible." That is, we are not trying to defend against modules with incoherent namespaces, divergent ports and portdecls, etc.
WARNING: For this transform to be sound, the submodule must have its ports properly declared as INPUT or OUTPUT ports. We do NOT try to handle inout ports. Why? Well, here is our basic strategy. If we have a module like:
module mymod ( output o, input a, input b ) ; ... endmodule
And we want to inline an instance such as:
mymod myinst (w, 1'b1, c + d) ;
Then the basic idea is to replace myinst with:
assign w = mangled_o; assign mangled_a = 1'b1; assign mangled_b = c + d; [... mangled body of mymod ...]
These assignment statements are unidirectional and if, for instance, you incorrectly mark an output as an input, then the assignment will flow in the wrong way. This use of assignment statements is particularly simpleminded. We have considered doing something smarter to avoid temporaries, but it seems like a very tricky problem in general so we think it's best not to get too clever.