Defcycle
Create a FSM from a design and a clock cycle specification, along with a signal name list.
Here is an example invocation of defcycle:
(defcycle my-clock-cycle
:design *my-sv-design*
:phases
(list (make-svtv-cyclephase :constants '(("my-clock" . 0))
:inputs-free t
:outputs-captured t)
(make-svtv-cyclephase :constants '(("my-clock" . 1))))
:names
'((input0 . "my-input")
(internal-val . "my-modinst[3].my_internal_signal")
(output . "my-output"))
:rewrite-phases t
:rewrite-cycle t
:cycle-simp t
:stobj svtv-data)
This form creates a clock cycle FSM for the given design, setting the signal
"my-clock" to 0 in the first phase (at which time input signals are
provided and outputs captured) and 1 in the second phase. It also provides
short names input0, internal-val, and output for some signals
that are given as hierarchical Verilog names. The rest of the arguments shown
are shown as their default values:
- :rewrite-phases if t applies SVEX rewriting to the
composed single phase FSM
- :rewrite-cycle if t applies SVEX rewriting to the composed cycle
FSM
- :cycle-simp should be a svex-simpconfig object, that is, t,
nil, or a natural number, controlling simplification that is applied while
composing the cycle. Here nil signifies that no simplification is
performed, t signifies that constants are propagated and cheap
simplifications applied to concatenation, select, and shift operations, and a
natural number says that full rewriting will be applied during composition with
that number as the iteration limit (the clk argument of
svex-rewrite-fncall).
- :stobj allows the event to use another stobj congruent to
svtv-data rather than svtv-data itself.
