Vwsim-hdl
The VWSIM Hardware Description Language (HDL).
Introduction
VWSIM accepts heirarchical netlist descriptions in its native
LISP-style format. Here, we describe the expected syntax of a
netlist described using the VWSIM HDL. At a high-level, a netlist
is a list of modules where each module consists of a name,
input/output nodes, and a list of occurrences. An occurrence is
either a primitive device (resistor, inductor, etc.) or an
instantiation of a defined module. Below, the primitives are
described first, followed by occurrences, modules, and
netlists.
Unlike SPICE, VWSIM HDL separates the circuit netlist
description from it associated simulation commands (e.g.,
simulation times, print requests). Such simulation-control
commands are provided as arguments when invoking the simulator.
VWSIM offers a collection of primitive circuit models, which are
combined into a single model for eventual circuit simulation.
Below we describe the circuit primitives to which all models must
eventually be expanded; these basic circuit models have
mathematical descriptions based in circuit theory and physics. In
a companion document, we provide a description of each circuit
element and its associated mathematical model (as used by the VWSIM
system).
Note: see vwsim-names for the expected format of device
and node names when defining netlists.
Primitive device
A primitive, in the VWSIM Lisp format, is one of the following.
Other input formats will be converted into this format.
Voltage Source
(name v (pos neg) (branch) (term))
where
- pos is the node connected to the positive terminal.
- neg is the node connected to the negative terminal.
- branch is the name for the current through the
device.
- term is a vwsim-term.
Current Source
(name i (pos neg) (branch) (term))
where
- pos is the node connected to the positive terminal.
- neg is the node connected to the negative terminal.
- branch is the name for the current through the
device.
- term is a vwsim-term.
Phase Source
(name p (pos neg) (branch) (term))
where
- pos is the node connected to the positive terminal.
- neg is the node connected to the negative terminal.
- branch is the name for the current through the
device.
- term is a vwsim-term.
Resistor
(name r (pos neg) (branch) (resistance))
where
- pos is the node connected to the positive terminal.
- neg is the node connected to the negative terminal.
- branch is the name for the current through the
device.
- resistance (in Ohms) is a quoted positive rational.
Inductor
(name l (pos neg) (branch) (inductance))
where
- pos is the node connected to the positive terminal.
- neg is the node connected to the negative terminal.
- branch is the name for the current through the
device.
- inductance (in Henries) is a quoted positive
rational.
Capacitor
(name c (pos neg) (branch) (capacitance))
where
- pos is the node connected to the positive terminal.
- neg is the node connected to the negative terminal.
- branch is the name for the current through the
device.
- capacitance (in Farads) is a quoted positive
rational.
Josephson Junction
(name b (pos neg) (branch) (icrit area vg rn r0 cap))
where
- pos is the node connected to the positive terminal.
- neg is the node connected to the negative terminal.
- branch is the name for the voltage or phase through
the device depending on the simulation type.
- icrit is the JJ critical current; it is a quoted
positive rational.
- area is the JJ area; it is a quoted
positive rational.
- vg is the JJ gap voltage; it is a quoted
positive rational.
- rn is the JJ normal resistance; it is a quoted
positive rational.
- r0 is the JJ subgap resistance; it is a quoted
positive rational.
- cap is the JJ capacitance; it is a quoted
positive rational.
Mutual Inductance
(name k (inductor0-name inductor1-name) (coupling-factor))
where
- inductor0-name is the name of the first coupled
inductor. The coupled inductors are expected to be in the same
module.
- inductor1-name is the name of the second coupled
inductor.
- coupling-factor is a vwsim-term; it is a quoted
rational between -1 and 1, inclusive.
Transmission Line
(name t (pos0 neg0 pos1 neg1) (br0 br1) (delay impedance))
where
- pos0 is the node connected to the positive terminal
at the first port.
- neg0 is the node connected to the negative terminal
at the first port.
- pos1 is the node connected to the positive terminal
at the second port.
- neg1 is the node connected to the negative terminal
at the second port.
- br0 is the name for the current through the first
port.
- br0 is the name for the current through the second
port.
- delay is the time delay (in seconds) of the
transmission line; it is a quoted rational.
- impedance is the transmission line impedance (in
Ohms); it is a quoted rational.
Occurrence
An occurrence is one of the following:
- A primitive device
- A module reference of the form:
(name module-name module-IOs)
where
- module-name is the name of the module being
referenced.
- module-IOs is a list of nodes that will be passed
to and substituted into the module reference.
Module
A module defines an unordered collection of references to
primitives and inferior modules. A module is of the following
form:
(name module-IOs occurrences)
where
- module-IOs is a list of external node (wire
connections) placeholders that will be available to the module
occurrences. Connections to internal node names will be
provided when a module is referenced by a superior
occurrence (reference).
- occurrences is a list of occurrences.
Netlist
A netlist is an ordered list of modules. The netlist is defined such that
- The first module is the top-level circuit.
- Each module is defined only once.
- Each (interior) module occurrence that references another module may
reference a module defined later in the netlist.
When VWSIM processes an input model, it attempts to assure that all
module references are valid.
See vwsim for a flowchart of how this input model is
processed for simulation.
Subtopics
- Vwsim-term
- The VWSIM Mathematical Term Language.
- Vwsim-constants
- The constants used by the VWSIM simulator.
