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RISC-V features.
The RISC-V ISA is really a family of ISAs: there is a choice of base (RV32I, RV64I, RV32E, RV64E), and there are choices of extensions. There is also a choice of little or big endian memory access (for data; instruction access is always little endian [ISA:1.5.1]). Perhaps less obvious, there is also a choice of which parts of the address space are readable and/or writable.
For a general model of the RISC-V ISA, we want to accommodate all the possible choices. Towards that goal, we introduce a notion of `features', which define these choices; we start with only some choices, which we plan to extend it with more choices.