|
|
|---|
|
|
|
|---|
Fix up type (signedness) information between port and variable declarations.
This is a very early transform that should be run almost immediately. It needs to be run after make-implicit-wires. It is ordinarily run as part of vl-annotate-design.
Port and variable declarations have a strange overlap with certain
subtleties. In some cases, the port declaration is "complete" and also gives
rise to a net declaration. For instance, the declaration of
module mymod (a, b, c, ...) ;
input wire [3:0] a; // <-- combined port and net declaration
// illegal to subsequently declare wire [3:0] a.
endmodule
In other cases, the port declaration is "incomplete," and it is legal
to subsequently declare the same name as a net or variable. For instance,
the following is valid even though it looks like
module mymod (a, b, c, ...) ; input [3:0] b; // <-- port declaration wire [3:0] b; // <-- corresponding net declaration endmodule
But incomplete port declarations do not require that an corresponding net
declaration be explicitly present. For instance, if we simply omit the
A particularly subtle part of this is that signedness information can be given in either the port or the net declaration. For instance:
module mymod (a, b, c, d, ...) ; input [3:0] c; // c becomes signed because the wire signed [3:0] c; // net declaration says so input signed [3:0] d; // d becomes signed because the wire [3:0] d; // port declaration says so endmodule
To cope with this, after introducing implicit wires, we cross-propagate type information between incomplete port declarations and their corresponding net declarations. The general goal is to ensure that the types of the ports and nets agree and are correct by the time actual modules are produced.