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Discussion of creating svex assignments from combinational/latch-style always blocks.
Verilog and SystemVerilog don't always cleanly translate to a finite-state-machine semantics, especially when it comes to always blocks that behave as latches. We discuss some of the choices we made in this translation.
It isn't clear how Verilog simulators distinguish between these constructs. For a simple latch of the form
always_latch if (en) q = d;
Verilog simulators produce identical results if the