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Representation of a single port.
This is a ``transparent'' sum type introduced using deftranssum. It is simply any one of the following types:
Most ports are regular ports, see vl-regularport. However, SystemVerilog also adds interface ports, see vl-interfaceport.
It is generally best to avoid using port names except perhaps for things like error messages. Why? As shown above, some ports might not have names, and even when a port does have a name, it does not necessarily correspond to any wires in the module. Since these cases are exotic, code that is based on port names is likely to work for simple test cases, but then fail later when more complex examples are encountered!
Usually you should not need to deal with port names. The argresolve transform converts module instances that use named arguments into their plain equivalents, and once this has been done there really isn't much reason to have port names anymore. Instead, you can work directly with the port's expression.
Our
A "blank" port expression (represented by
The direction of a port can most safely be obtained by vl-port-direction. Note that directions are not particularly reliable in Verilog: one can assign to a input or read from an output, and in simulators like Cadence this can actually impact values on wires in the supermodule as if the ports have no buffers. We call this "backflow." BOZO eventually implement a comprehensive approach to detecting and dealing with backflow.
The width of a port can be determined after expression sizing has been performed by examining the width of the port expression. See expression-sizing for details.