• Top
    • Documentation
    • Books
    • Boolean-reasoning
    • Projects
    • Debugging
    • Std
    • Proof-automation
    • Macro-libraries
    • ACL2
    • Interfacing-tools
    • Hardware-verification
      • Gl
      • Esim
      • Vl2014
      • Sv
      • Fgl
      • Vwsim
      • Vl
        • Syntax
        • Loader
          • Preprocessor
          • Vl-loadconfig
          • Vl-loadstate
          • Lexer
          • Parser
            • Parse-expressions
            • Parse-udps
            • Parse-statements
            • Parse-property
            • Vl-genelements
            • Parse-paramdecls
            • Parse-blockitems
            • Parse-utils
            • Parse-insts
            • Parse-functions
            • Parse-assignments
            • Parse-clocking
            • Parse-strengths
            • Vl-parse-genvar-declaration
            • Vl-parse
            • Parse-netdecls
            • Parse-asserts
            • Vl-maybe-parse-lifetime
            • Parse-dpi-import-export
            • Parse-ports
              • Parse-port-types
              • Creating-portdecls/vardecls
              • Verilog-2005-ports
              • Sv-non-ansi-portdecls
              • Vl-parse-ansi-port-declaration-2005
              • Vl-parse-1+-port-declarations-separated-by-commas-2005
              • Vl-parse-ansi-port-declaration
              • Vl-parse-1+-ansi-port-declarations
              • Verilog-2005-portdecls
            • Parse-timeunits
            • Seq
            • Parse-packages
            • Parse-eventctrl
          • Vl-load-merge-descriptions
          • Vl-find-basename/extension
          • Vl-load-file
          • Vl-loadresult
          • Scope-of-defines
          • Vl-find-file
          • Vl-flush-out-descriptions
          • Vl-description
          • Vl-read-file
          • Vl-includeskips-report-gather
          • Vl-load-main
          • Extended-characters
          • Vl-load
          • Vl-load-description
          • Vl-descriptions-left-to-load
          • Inject-warnings
          • Vl-preprocess-debug
          • Vl-write-preprocessor-debug-file
          • Vl-read-file-report-gather
          • Vl-load-descriptions
          • Vl-load-files
          • Translate-off
          • Vl-load-read-file-hook
          • Vl-read-file-report
          • Vl-loadstate-pad
          • Vl-load-summary
          • Vl-collect-modules-from-descriptions
          • Vl-loadstate->warnings
          • Vl-iskips-report
          • Vl-descriptionlist
        • Warnings
        • Getting-started
        • Utilities
        • Printer
        • Kit
        • Mlib
        • Transforms
      • X86isa
      • Svl
      • Rtl
    • Software-verification
    • Math
    • Testing-utilities
  • Parser

Parse-ports

Functions for parsing Verilog and SystemVerilog ports.

Subtopics

Parse-port-types
Handling of SystemVerilog-2012 port types.
Creating-portdecls/vardecls
Utilities for the initial creation of port declarations and (if the port declaration is complete) corresponding net declarations.
Verilog-2005-ports
Parsing for Verilog-2005 ports.
Sv-non-ansi-portdecls
Parsing of SystemVerilog-2012 non-ANSI port declarations.
Vl-parse-ansi-port-declaration-2005
Matches a port declaration (which may involve several comma-separated variable names), and creates an ansi-portdecl object for each of them.
Vl-parse-1+-port-declarations-separated-by-commas-2005
Verilog-2005 Only. Matches port_declaration { ',' port_declaration } in ansi style port lists. Creates ansi-portdecls.
Vl-parse-ansi-port-declaration
Matches ansi_port_declaration. Peeks at the token after to make sure it's a comma or right paren, but doesn't consume it.
Vl-parse-1+-ansi-port-declarations
Matches {attribute_instance} ansi_port_declaration { ',' {attribute_instance} ansi_port_declaration }
Verilog-2005-portdecls
Parsing for Verilog-2005 port declarations.