Defsvtv
(Deprecated) Create an SVTV structure for some simulation pattern of a hardware design.
This is deprecated in favor of defsvtv$.
See the sv-tutorial and the parent topic svex-stvs for
higher-level discussion; here, we provide a reference for the arguments.
- :design or :mod provides the SVEX design object containing
the hierarchical hardware model. One or the other of :design or :mod
should be given, but not both; they mean exactly the same thing.
- :inputs provide the stimulation pattern for inputs to the module,
formatted as discussed in svtv-stimulus-format. The argument is
evaluated, so if you want to write your stimulus as a literal (as opposed to
referencing a constant or generating it via a function call) you should put a
quote in front of it; you may also use backquote syntax.
- :overrides are similar to :inputs and take the same syntax, but
are expected to refer to signals that are already driven. For signals that are
overridden, in the cycle that a variable or value is provided, that signal's
driving expressions will be disconnected and it will instead be forced to the
given value.
- :outputs and :internals are treated interchangeably; both specify
what signals should be extracted and at what phases of simulation.
- :parents, :short, :long, and :labels pertain to
documentation; if any of :parents, :short, or :long are given
then additional xdoc will also be generated to show a timing diagram.
:labels, if provided, label the phases in that timing diagram.
- :simplify is T by default; it can be set to NIL to avoid rewriting the
output svex expressions, which may be desirable if you are doing a
decomposition proof.
- :initial-state-vars is NIL by default; it can be set to T to set the
initial state of the simulation to all free variables instead of all Xes.
- :keep-final-state is NIL by default; it can be set to T to store the
state after the final phase in the SVTV as (svtv->nextstate svtv).
- :keep-all-states is NIL by default; it can be set to T to store the
sequence of nphases+1 states in the SVTV as (svtv->states svtv).
- :state-machine is NIL by default; if set to T, it is the same as
setting :initial-state-vars and keep-final-state to T.
Subtopics
- Defsvtv-main
- Main subroutine of defsvtv, which extracts output formulas from
the provided design.
- Svtv-stimulus-format
- (Deprecated) Syntax for inputs/outputs/overrides/internals entries of defsvtv forms
- Defstv
- Same as defsvtv.
