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Fixtype of RISC-V feature choices for endianness.
This is a tagged union type, introduced by fty::deftagsum.
Although instruction encodings are always in little endian [ISA:1.5], data loaded/stored from/to memory may be little or big endian [ISA:2.6]. This choice is ``byte-address invariant'' [ISA:2.6], i.e. it does not depend on the address; so there is just one choice for the whole memory.