Instructions
Model of instructions.
We introduce fixtypes that define essentially
an abstract syntax of RISC-V instructions.
This only exists in the model, not in the processor,
which represents instructions in binary.
These high-level instructions are the result of decoding the binary format;
they are close in spirit to assembly instructions.
We start with the unprivileged instructions
in RV32I [ISA:2] and RV64I [ISA:4],
which are the same for RV32E and RV64E [ISA:3],
except for FENCE, ECALL, EBREAK, and HINT.
We also cover the instructions for the M extension [ISA:12].
We plan to add privileged instructions,
as well as instructions for more extensions.
Not all the instructions defined here are valid
in every instantiation of the RISC-V ISA.
For example, ADDIW is only valid when the base is RV64I or RV64E,
and MUL is only valid with the M extension.
We define a predicate saying which instructions are valid
with respect to given features.
Subtopics
- Instr
- Fixtype of instructions.
- Op-funct
- Fixtype of names of instructions with the OP opcode
[ISA:2.4.2] [ISA:12.1] [ISA:12.2].
- Op-32-funct
- Fixtype of names of instructions with the OP-32 opcode
[ISA:4.2.2] [ISA:12.1] [ISA:12.2].
- Op-imm-funct
- Fixtype of
names of non-shift instructions with the OP-IMM opcode
[ISA:2.4.1].
- Load-funct
- Fixtype of names of instructions with the LOAD opcode
[ISA:2.6] [ISA:4.3].
- Instr-validp
- Check if an instruction is valid with respect to given features.
- Branch-funct
- Fixtype of names of instructions with the BRANCH opcode
[ISA:2.5.2].
- Op-imms-funct
- Fixtype of names of shift instructions with the OP-IMM opcode
[ISA:2.4.1].
- Store-funct
- Fixtype of names of instructions with the STORE opcode
[ISA:2.6] [ISA:4.3].
- Op-imms-32-funct
- Fixtype of
names of shift instructions with the OP-IMM-32 opcode
[ISA:4.2.1].
- Instr-option
- Fixtype of optional instructions.
- Op-imm-32-funct
- Fixtype of
names of non-shift instructions with the OP-IMM-32 opcode
[ISA:4.2.1].
