Features
RISC-V features.
The RISC-V ISA is really a family of ISAs:
there is a choice of base (RV32I, RV64I, RV128I, RV32E, RV64E),
and there are choices of extensions.
There is also a choice of little or big endian memory access
(for data; instruction access is always little endian [ISA:1.5]).
Perhaps less obvious, there is also a choice of
which parts of the address space are readable and/or writable.
For a general model of the RISC-V ISA,
we want to accommodate all the possible choices.
Towards that goal, we introduce a notion of `features',
which define these choices;
we start with only some choices,
which we plan to extend with more choices.
Subtopics
- Feat-base
- Fixtype of RISC-V feature choices for the base.
- Feat-endian
- Fixtype of RISC-V feature choices for endianness.
- Feat
- Fixtype of RISC-V feature choices.
- Feat->xlen
- The XLEN parameter [ISA:1.3].
- Feat->ialign
- The IALIGN parameter [ISA:1.5].
- Feat->xnum
- The number of x registers.
- Feat-64p
- Check if the features indicate 64 bits.
- Feat-32p
- Check if the features indicate 32 bits.
- Feat-little-endianp
- Check if the features indicate little endian.
- Feat-big-endianp
- Check if the features indicate bit endian.
- Feat->ilen
- The ILEN parameter [ISA:1.5].
- Feat-embedp
- Check if the features indicate embedded systems.
- Feat-mp
- Check if the features indicate the M extension.
