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• Primitives

*vl-1-bit-notif0*

Primitive conditional driver.

The Verilog meaning of this module is:

module VL_1_BIT_NOTIF0 (out, data, ctrl);
   output out;
   input data;
   input ctrl;
   assign out = ctrl ? 1'bz : ~data;
endmodule

VL takes this as a primitive. The gate-elim transform converts certain notif0 gates into instances of this module.

The corresponding esim primitive is ACL2::*esim-notif0*.

Definition: *vl-1-bit-notif0*

(defconst *vl-1-bit-notif0*
 (b*
  ((name "VL_1_BIT_NOTIF0")
   (atts '(("VL_PRIMITIVE") ("VL_HANDS_OFF")))
   ((mv out-expr
        out-port out-portdecl out-vardecl)
    (vl-primitive-mkport "out" :vl-output))
   ((mv data-expr
        data-port data-portdecl data-vardecl)
    (vl-primitive-mkport "data" :vl-input))
   ((mv ctrl-expr
        ctrl-port ctrl-portdecl ctrl-vardecl)
    (vl-primitive-mkport "ctrl" :vl-input))
   (assign
    (make-vl-assign
         :lvalue out-expr
         :expr
         (make-vl-nonatom
              :op :vl-qmark
              :args (list ctrl-expr |*sized-1'bz*|
                          (make-vl-nonatom :op :vl-unary-bitnot
                                           :args (list data-expr)
                                           :finalwidth 1
                                           :finaltype :vl-unsigned))
              :finalwidth 1
              :finaltype :vl-unsigned)
         :loc *vl-fakeloc*)))
  (hons-copy
       (make-vl-module
            :name name
            :origname name
            :ports (list out-port data-port ctrl-port)
            :portdecls (list out-portdecl
                             data-portdecl ctrl-portdecl)
            :vardecls (list out-vardecl data-vardecl ctrl-vardecl)
            :assigns (list assign)
            :minloc *vl-fakeloc*
            :maxloc *vl-fakeloc*
            :atts atts
            :esim acl2::*esim-notif0*))))