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• Primitives

*vl-1-bit-xnor*

Primitive xnor-gate module.

The Verilog definition of this module is:

module VL_1_BIT_XNOR (out, a, b) ;
  output out;
  input a;
  input b;
  assign out = ~(a ^ b);
endmodule

VL takes this as a primitive. We use this in place of xnor gates, but probably not much else.

The corresponding esim primitive is ACL2::*esim-xnor*

Definition: *vl-1-bit-xnor*

(defconst *vl-1-bit-xnor*
 (b*
  ((name "VL_1_BIT_XNOR")
   (atts '(("VL_PRIMITIVE") ("VL_HANDS_OFF")))
   ((mv out-expr
        out-port out-portdecl out-vardecl)
    (vl-primitive-mkport "out" :vl-output))
   ((mv a-expr a-port a-portdecl a-vardecl)
    (vl-primitive-mkport "a" :vl-input))
   ((mv b-expr b-port b-portdecl b-vardecl)
    (vl-primitive-mkport "b" :vl-input))
   (assign
    (make-vl-assign
        :lvalue out-expr
        :expr
        (make-vl-nonatom
             :op :vl-unary-bitnot
             :args (list (make-vl-nonatom :op :vl-binary-xor
                                          :args (list a-expr b-expr)
                                          :finalwidth 1
                                          :finaltype :vl-unsigned))
             :finalwidth 1
             :finaltype :vl-unsigned)
        :loc *vl-fakeloc*)))
  (hons-copy
       (make-vl-module
            :name name
            :origname name
            :ports (list out-port a-port b-port)
            :portdecls (list out-portdecl a-portdecl b-portdecl)
            :vardecls (list out-vardecl a-vardecl b-vardecl)
            :assigns (list assign)
            :minloc *vl-fakeloc*
            :maxloc *vl-fakeloc*
            :atts atts
            :esim acl2::*esim-xnor*))))