Processor Architectures

• "Scalable Selective Re-execution for EDGE Architectures," R. Desikan, L. Sethumadhavan, D. Burger, and S.W. Keckler, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October, 2004. PS, PDF

• "Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures,", R. Nagarajan, S.K. Kushwaha, D. Burger, K. McKinley, C. Lin, and S.W. Keckler, International Conference on Parallel Architectures and Compilation Techniques (PACT), September, 2004. PS, PDF

• "Scaling to the End of Silicon with EDGE Architectures," D. Burger, S.W. Keckler, K.S. McKinley, M. Dahlin, L.K. John, Calvin Lin, C.R. Moore, J. Burrill, R.G. McDonald, and W. Yoder, IEEE Computer, 37:7, pp. 44-55, July, 2004.

• "Universal Mechanisms for Data-Parallel Architectures," K. Sankaralingam, S.W. Keckler, W. Mark, and D.C. Burger, 2003 International Symposium on Microarchitecture (MICRO), pp. 303-314, December, 2003. PS, PDF

• "Scalable Hardware Memory Disambiguation for High-ILP Processors," L. Sethumadhavan, R. Desikan, D.C. Burger, C.R. Moore, and S.W. Keckler, International Symposium on Microarchitecture (MICRO), pp. 399-410, December, 2003. PS, PDF

• "Routed Inter-ALU Networks for ILP Scalability and Performance," K. Sankaralingam, V.A. Singh, S.W. Keckler, and D. Burger, International Conference on Computer Design (ICCD), pp. 170-177, October, 2003. PS, PDF

• "Exploiting ILP, DLP, and TLP Using Polymorphism in the TRIPS Architecture," K. Sankaralingam, R. Nagarajan, H. Liu, J. Huh, C.K. Kim D. Burger, S.W. Keckler, and C.R. Moore, 30th Annual International Symposium on Computer Architecture (ISCA), pp. 422-433, June 2003. PS, PDF

• "Lightweight Distributed Selective Re-Execution and its Implications for Value Speculation," R. Desikan, L. Sethumadhavan, R. Nagarajan, D.C. Burger, and S.W. Keckler. 1st Value Prediction Workshop, at ISCA-30, June, 2003.

• "Design and Analysis of Routed Inter-ALU Networks for ILP Scalability and Performance," V.A. Singh, K Sankaralingam, S.W. Keckler, and D.C. Burger, TR-03-17. Department of Computer Sciences, The University of Texas at Austin, May, 2003.

• "A Routing Network for the Grid Processor Architecture," V.A. Singh, S.W. Keckler, and D.C. Burger. TR-03-10, Department of Computer Sciences, The University of Texas at Austin, April, 2003.

• "A Wire-Delay Scalable Microprocessor Architecture for High Performance Systems," S.W. Keckler, Doug Burger, C.R. Moore, R. Nagarajan, K. Sankaralingam, V. Agarwal, M.S. Hrishikesh, N. Ranganathan, and P. Shivakumar. International Solid-State Circuits Conference (ISSCC), pp. 1068-1069, February, 2003. PDF

• "Combining Hyperblocks and Exit Prediction to Increase Front-End Bandwidth and Performance," N. Ranganathan, D. Jimenez, R. Nagarajan, D.C. Burger, S.W. Keckler, and C. Lin. TR-02-41, Department of Computer Sciences, The University of Texas at Austin, September, 2002.

• "A Design Space Evaluation of Grid Processor Architectures," R. Nagarajan, K. Sankaralingam, D. Burger, and S.W. Keckler. 34th Annual International Symposium on Microarchitecture (MICRO), pp. 40-51, December, 2001. PS, PDF

• "A Technology-Scalable Architecture for Fast Clocks and High ILP," K. Sankaralingam, R. Nagarajan, D. Burger, and S.W. Keckler. in Interaction Between Compilers and Computer Architectures, edited by G. Lee and P. Yew, pp. 117-139, Kluwer Academic Publishers, 2001. PS, PDF

• "A Technology-Scalable Architecture for Fast Clocks and High ILP," K. Sankaralingam, R. Nagarajan, D.C. Burger, S.W. Keckler. 5th Workshop on the Interaction of Compilers and Computer Architecture, at HPCA-7, January, 2001.

• "A Technology-Scalable Architecture for Fast Clocks and High ILP," K. Sankaralingam, R. Nagarajan, D. Burger, and S.W. Keckler. TR-01-02, Department of Computer Sciences, The University of Texas at Austin, January, 2001. PDF

• "The Impact of Delay on the Design of Branch Predictors," D.A. Jiménez, S.W. Keckler, and C. Lin. 33rd International Symposium on Microarchitecture (MICRO), pp. 67-76, December 2000. PS, PDF

• "Concurrent Event Handling Through Multithreading," S.W. Keckler, A. Chang, W.S. Lee, S. Chatterjee, and W.J. Dally. IEEE Transactions on Computers, 48:9, September, 1999, pp 903-916. PDF

• "The Effects of Explicitly Parallel Mechanisms on the Multi-ALU Processor Cluster Pipeline," A. Chang, W.J. Dally, S.W. Keckler, N.P. Carter, and W.S. Lee. International Conference on Computer Design (ICCD), pp. 474-481, October 1998. PS, PDF

• "Exploiting Fine-Grain Thread Level Parallelism on the MIT Multi-ALU Processor," S.W. Keckler, W.J. Dally, D. Maskit, N.P. Carter, A. Chang, and W.S Lee. 25th Annual International Symposium on Computer Architecture (ISCA), pp. 306-317, July 1998. PS, PDF

• "The MIT Multi-ALU Processor," S.W. Keckler, W.J. Dally, A. Chang, N.P. Carter, and W.S Lee. Proceedings of Hot Chips IX, pp. 1-8, August 1997. PS, PDF

• "Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism," S.W. Keckler, and W.J. Dally. International Symposium on Computer Architecture (ISCA), pp. 202-213, May 1992. PS, PDF

• "Exploiting Microarchitectural Redundancy For Defect Tolerance," P. Shivakumar, S.W. Keckler, C.R. Moore, and D. Burger, International Conference on Computer Design (ICCD), pp. 481-488, October, 2003. PS, PDF

• "Exploiting Microarchitectural Redundancy For Defect Tolerance," P. Shivakumar, S.W. Keckler, C.R. Moore, and D.C. Burger, IBM Austin Center for Advanced Studies Conference, February, 2003.

• "Modeling the Effect of Technology Trends on Soft Error Rate of Combinational Logic," P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, and L. Alvisi. 2002 International Conference on Dependable Systems and Networks (DSN), pp. 389-398, June, 2002. PS, PDF

• "Modeling the Impact of Device and Pipeline Scaling on the Soft Error Rate of Processor Elements," P. Shivakumar, M. Kistler, S.W. Keckler, D.C. Burger, and L. Alvisi. TR-02-19, Department of Computer Sciences, The University of Texas at Austin, April, 2002.

• "Modeling the Effect of Technology Trends on Soft Error Rate of Combinational Logic," P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, and L. Alvisi, IBM Austin Center for Advanced Studies Workshop, February, 2002.

• "The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays," M.S. Hrishikesh, N.P. Jouppi, K.I. Farkas, D. Burger, S.W. Keckler, and P. Shivakumar. 29th International Symposium on Computer Architecture (ISCA), pp. 14-24, May, 2002. PS, PDF

• "Impact of Technology Scaling on Instruction Execution Throughput," M.S. Hrishikesh, D.C. Burger, and S.W. Keckler. TR-00-06, Department of Computer Sciences, The University of Texas at Austin, June, 2001. PS, PDF

• "The Effect of Technology Scaling on Microarchitectural Structures," V. Agarwal, S.W. Keckler, and D.C. Burger. TR-00-02, Department of Computer Sciences, The University of Texas at Austin, May, 2001. PS, PDF

• "Clock Rate Versus IPC: The End of the Road for Conventional Microarchitectures," V. Agarwal, M.S. Hrishikesh, S.W. Keckler, and D. Burger. 27th International Symposium on Computer Architecture (ISCA), June, 2000. PS, PDF

• "Technology Independent Area and Delay Estimates for Microprocessor Building Blocks," S. Gupta, S.W. Keckler, D.C. Burger. TR-00-05, Department of Computer Sciences, The University of Texas at Austin, May, 2000. PS, PDF

• "Fast Thread Communication and Synchronization Mechanisms for a Scalable Single Chip Multiprocessor", S.W. Keckler. PhD Thesis, Massachusetts Institute of Technology, May 1998. PS

• "A Coupled Multi-ALU Processing Node for a Highly Parallel Computer", S.W. Keckler. MS Thesis, Artificial Intelligence Laboratory Technical Report 1355, Massachusetts Institute of Technology, May 1992. PS

• "Exploring the Design Space of Future CMPs," J. Huh, D. Burger, and S.W. Keckler. International Symposium on Parallel Architectures and Compilation Techniques (PACT), pp. 199-210, September, 2001. PS, PDF

• "Maximizing Performance/Area Implementations for Future Single-Chip Servers," J. Huh, D.C. Burger, and S.W. Keckler. IBM Austin Center for Advanced Studies Workshop, January, 2001.

• "Processor Mechanisms for Software Shared Memory," N.P. Carter, W.J. Dally, W.S. Lee, S.W. Keckler, and A. Chang. International Symposium on High Performance Computing, October 2000. PDF

• "Efficient Protected Message Interface in the MIT M-Machine," W.S. Lee, W.J. Dally, S.W. Keckler, N.P. Carter, and A. Chang. IEEE Computer, pp. 69-75, November 1998. PDF

• "The M-Machine Multicomputer," M. Fillo, S.W. Keckler, W.J. Dally, N.P. Carter, A. Chang, Y. Gurevich, and W.S Lee. International Journal of Parallel Programming, 25:3, pp. 183-212, June 1997.

• "The M-Machine Multicomputer," M. Fillo, S.W. Keckler, W.J. Dally, N.P. Carter, A. Chang, Y. Gurevich, and W.S Lee. Proceedings of the 28th Annual International Symposium on Microarchitecture (MICRO), pp. 146-156, December 1995. PS, PDF

• "On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories," R. Desikan, C.R. Lefurgy, S.W. Keckler, D.C. Burger, IBM Austin Center for Advanced Studies Conference, February, 2003.

• "An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches," C. Kim, D. Burger, and S.W. Keckler. 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 211-222, October, 2002. PS, PDF

• "On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories," R. Desikan, S.W. Keckler, and D.C. Burger. TR-02-47, Department of Computer Sciences, The University of Texas at Austin, September, 2002.

• "An Adaptive Cache Structure for Future High-Performance Systems," C. Kim, D. Burger, and S.W. Keckler. IBM Austin Center for Advanced Studies Workshop, February, 2002.

• "An Adaptive Cache Structure for Future High-Performance Systems," C. Kim, D.C. Burger, and S.W. Keckler. TR-02-10, Department of Computer Sciences, The University of Texas at Austin, February, 2002.

• "Assessment of MRAM Technology Characteristics and Architectures," R. Desikan, S.W. Keckler, and D.C. Burger. TR-01-36, Department of Computer Sciences, The University of Texas at Austin, October, 2001.

• "Hardware Support for Fast Capability-based Addressing," N.P. Carter, S.W. Keckler, and W.J. Dally. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 319-327, October 1994. PS, PDF

• "Microprocessor Pipeline Energy Analysis," R. Natarajan, H. Hanson, S.W. Keckler, C.R. Moore, and D. Burger, IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 282-287, August, 2003. PS, PDF

• "Static Energy Reduction Techniques for Microprocessor Caches," H. Hanson, M.S. Hrishikesh, V. Agarwal, S.W. Keckler, and D. Burger. IEEE Transactions on VLSI Systems, 11(3):303-313, June, 2003.
• "Static Energy Reduction Techniques for Microprocessor Caches," H. Hanson, M.S. Hrishikesh, V. Agarwal, S.W. Keckler, and D. Burger. International Conference on Computer Design (ICCD), pp. 276-283, September, 2001. PS, PDF

• "Static Energy Reduction Techniques in Microprocessor Caches," H. Hanson, S.W. Keckler, and D.C. Burger. TR-01-18, Department of Computer Sciences, The University of Texas at Austin, June, 2001.

• "Measuring Experimental Error in Microprocessor Simulation," R. Desikan, D. Burger, and S.W. Keckler. 28th International Symposium on Computer Architecture (ISCA), pp. 266-277, June 2001. PS, PDF

• "Sim-alpha: a Validated, Execution-Driven Alpha 21264 Simulator," R. Desikan, D.C. Burger, S.W. Keckler, and T.M. Austin. TR-01-23, Department of Computer Sciences, The University of Texas at Austin, October, 2001.

• "SimpleScalar Simulation of the PowerPC Instruction Set Architecture," K. Sankaralingam, R. Nagarajan, S.W. Keckler, and D.C. Burger. TR-00-04, Department of Computer Sciences, The University of Texas at Austin, May, 2001. PS, PDF

• "A Characterization of Speech Recognition on Modern Computer Systems," K. Agaram, S.W. Keckler, and D. Burger. 4th Annual International Workshop in Workload Characterization , pp. 45-53, December, 2001. PS, PDF

• "Characterizing the SPHINX Speech Recognition System," K. Agaram, S.W. Keckler, and D.C. Burger. IBM Austin Center for Advanced Studies Workshop, January, 2001.

• "Characterizing the SPHINX Speech Recognition System," K. Agaram, S.W. Keckler, D.C. Burger. TR-00-33, Department of Computer Sciences, The University of Texas at Austin, December, 2000. PS, PDF

• "International Symposium on Computer Architecture 1992," S.W. Keckler and W.J. Dally. Scientific Information Bulletin, Office of Naval Research Asian Office, 17:4, October-December, 1992.