Yi-Shan Lu

Ph.D.
Department of Computer Science
The University of Texas at Austin
yishanlu AT utexas DOT edu

Honors

Research

I am interested in making parallel computing more accessible to programmers in different application fields so that more people can enjoy the performance gain from parallel computing. This involves programming languages, compilers, computer architectures and understanding of applications.

I work with Prof. Keshav Pingali in Intelligent Software Systems research group.

Projects

I would like to come up with programming models suitable for constrained optimization/constraint satisfaction algorithms. I am exploring such models by using the Galois framework to parallelize graph algorithms from the following application fields.

Selected Publications

Please see here for the full list of my publication.

Conference Papers

  1. Wenmian Hua, Yi-Shan Lu, Keshav Pingali, Rajit Manohar. Cyclone: A Static Timing and Power Engine for Asynchronous Circuits. In 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2020. (Best Paper Award) [pdf][slides][DOI]

  2. Vinicius Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato Ribas, André Reis. Unlocking Fine-Grain Parallelism for AIG Rewriting. In 37th International Conference on Computer-Aided Design (ICCAD), San Diego, CA, November 5-8, 2018. [pdf][DOI]

  3. Chad Voegele*, Yi-Shan Lu*, Sreepathi Pai, Keshav Pingali. Parallel Triangle Counting and k-Truss Identification using Graph-centric Methods. In IEEE/DARPA/Amazon Graph Challenge 2017 at IEEE High Performance Extreme Computing Conference (HPEC), Waltham, MA, September 12-14, 2017. (Graph Challenge Champion; *contributed equally) [pdf][slides][DOI]

Workshop Papers

  1. Jiayuan He, Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. interact: An Interactive Design Environment for Asynchronous Logic. In 4th Workshop on Open-Source EDA Technology (WOSET), November 4, 2021. [pdf]

  2. Udit Agarwal, Samira Ataei, Jiayuan He, Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. A Digital Flow for Asynchronous VLSI Systems: Status Update. In 3rd Workshop on Open-Source EDA Technology (WOSET), November 5, 2020. [pdf][slides][video]

  3. Yi-Shan Lu, Rajit Manohar, Keshav Pingali. Blitz: A Static Timing Analyzer Parallelized Using Operator Formulation. In Work-in-Progress Poster Session, Design Automation Conference (DAC WIP), July 23, 2020. [slides]

  4. Samira Ataei, Jiayuan He, Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. Toward a Digital Flow for Asynchronous VLSI Systems. In 2nd Workshop on Open-Source EDA Technology (WOSET), Westminster, CO, November 7, 2019. [pdf]

  5. Yi-Shan Lu, Samira Ataei, Jiayuan He, Wenmian Hua, Sepideh Maleki, Yihang Yang, Martin Burtscher, Keshav Pingali, Rajit Manohar. Parallel Tools for Asynchronous VLSI Systems. In 1st Workshop on Open-Source EDA Technology (WOSET), San Diego, CA, November 8, 2018. [pdf]

Journal Papers

  1. Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He, Sepideh Maleki, Keshav Pingali. An Open-Source EDA Flow for Asynchronous Logic. In IEEE Design & Test 38 (2), 27-37, January 2021. [DOI]

Book Chapters

  1. Lu Y.-S., Pingali K. (2018) Can parallel programming revolutionize EDA tools?. In Reis A., Drechsler R. (eds) Advanced Logic Synthesis. Springer, Cham. [DOI]

Professional Activities

Teaching

Service