Department of Computer Science
The University of Texas at Austin
yishanlu AT utexas DOT edu
I am interested in making parallel computing more accessible to programmers in different application fields so that more people can enjoy the performance gain from parallel computing. This involves programming languages, compilers, computer architectures and understanding of applications.
I work with Prof. Keshav Pingali in Intelligent Software Systems research group.
I would like to come up with programming models suitable for constrained optimization/constraint satisfaction algorithms. I am exploring such models by using the Galois framework to parallelize graph algorithms from the following application fields.
Electronic Design Automation (EDA): Hardware designers use EDA tools to synthesize circuit descriptions to final layouts for manufacturing. During the synthesis process, functionality should remain the same; timing constraints should be respected; and area, power consumption should be optimized. Since EDA algorithms work on circuits, naturally represented as graphs, and the parallelism is hard to know statically, how to parallelize EDA algorithms becomes challenging.
Graph analytics: Graph analytics are important to discover patterns in graph data. For example, k-truss decomposition can cluster nodes in a graph based on their shared links. Since graph analytics can be realized with various combinations of programming models and implementations, the tradeoff between programming productivity and implementation efficiency needs to be addressed.
Graph pattern matching: Certain properties emerge from groups but are not observed from constituent individuals. To enable such analyses on graph data, we can locate interesting regions using graph pattern matching, i.e. matching for a query graph to subgraphs in a data graph. By working directly with (sparse) graphs, we may be able to match graph patterns more efficiently than with matrix/tensor forms. Besides, this approach allows the matching to be fuzzy to various degrees. Graph pattern matching can be applied to network intrusion detection, bioinformatics and verification in VLSI, etc.
Wenmian Hua, Yi-Shan Lu, Keshav Pingali, Rajit Manohar. Cyclone: A Static Timing and Power Engine for Asynchronous Circuits. In 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2020. (Best Paper Award) [pdf][slides][DOI]
Vinicius Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato Ribas, André Reis. Unlocking Fine-Grain Parallelism for AIG Rewriting. In 37th International Conference on Computer-Aided Design (ICCAD), San Diego, CA, November 5-8, 2018. [pdf][DOI]
Chad Voegele*, Yi-Shan Lu*, Sreepathi Pai, Keshav Pingali. Parallel Triangle Counting and k-Truss Identification using Graph-centric Methods. In IEEE/DARPA/Amazon Graph Challenge 2017 at IEEE High Performance Extreme Computing Conference (HPEC), Waltham, MA, September 12-14, 2017. (Graph Challenge Champion; *contributed equally) [pdf][slides][DOI]
Jiayuan He, Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. interact: An Interactive Design Environment for Asynchronous Logic. In 4th Workshop on Open-Source EDA Technology (WOSET), November 4, 2021. [pdf]
Udit Agarwal, Samira Ataei, Jiayuan He, Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. A Digital Flow for Asynchronous VLSI Systems: Status Update. In 3rd Workshop on Open-Source EDA Technology (WOSET), November 5, 2020. [pdf][slides][video]
Yi-Shan Lu, Rajit Manohar, Keshav Pingali. Blitz: A Static Timing Analyzer Parallelized Using Operator Formulation. In Work-in-Progress Poster Session, Design Automation Conference (DAC WIP), July 23, 2020. [slides]
Samira Ataei, Jiayuan He, Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. Toward a Digital Flow for Asynchronous VLSI Systems. In 2nd Workshop on Open-Source EDA Technology (WOSET), Westminster, CO, November 7, 2019. [pdf]
Yi-Shan Lu, Samira Ataei, Jiayuan He, Wenmian Hua, Sepideh Maleki, Yihang Yang, Martin Burtscher, Keshav Pingali, Rajit Manohar. Parallel Tools for Asynchronous VLSI Systems. In 1st Workshop on Open-Source EDA Technology (WOSET), San Diego, CA, November 8, 2018. [pdf]
Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He, Sepideh Maleki, Keshav Pingali. An Open-Source EDA Flow for Asynchronous Logic. In IEEE Design & Test 38 (2), 27-37, January 2021. [DOI]
Lu Y.-S., Pingali K. (2018) Can parallel programming revolutionize EDA tools?. In Reis A., Drechsler R. (eds) Advanced Logic Synthesis. Springer, Cham. [DOI]