UTCS Colloquium/Architecture: Moinuddin Qureshi/ IBM T.J. Watson Research Center: "Scaling the Memory Wall with Phase Change Memories," ACES 2.402, Monday, November 2, 2009, 3:30 p.m.

Contact Name: 
Jenna Whitney
Date: 
Nov 2, 2009 3:30pm - 4:30pm

There is a sign-up schedule for this talk at http://www.cs.utex

as.edu/department/webevent/utcs/events/cgi/list_events.cgi

Type of Tal

k: UTCS Colloquium/Architecture

Speaker/Affiliation: Moinuddin Qureshi

/ IBM T.J. Watson Research Center

Date/Time: Monday, November 2, 200

9, 3:30 p.m.

Location: ACES 2.402

Host: Yale Patt

Talk Titl

e: "Scaling the Memory Wall with Phase Change Memories"

Talk Abstract:

DRAM has been the building block for main memory systems for several dec

ades. However, with each technology generation, significant portion of th

e total system power and the total system cost is spent in the DRAM memory

system, and this trend continues to grow making DRAM a less desirable choi

ce for future larger system memories. Therefore, architects and system des

igners must look at alternative technologies for growing memory capacity. P

hase-Change Memory (PCM) is an emerging technology which is denser than DRA

M and can boost memory capacity in a scalable and power-efficient manner.

However, PCM has it own unique challenges such as higher read latency (tha

n DRAM), much higher write latency, and limited lifetime due to write end

urance.

In this talk I will focus on architectural solutions that can
leverage the density and power-efficiency advantages of PCM while addressi

ng its challenges. I will propose a “Hybrid Memory” system that combines
PCM-based main memory with a DRAM buffer, thereby obtaining the capacity

benefits of PCM and latency benefits of DRAM. I will then describe a simple

, novel, and efficient wear leveling technique for PCM memories that obta

ins near-perfect lifetime while incurring a storage overhead of less than 1

3 bytes. Finally, I will provide extensions to PCM memories than can ada

ptively “cancel” or “pause” write requests to reduce latency of read re

quests when there is significant contention from the (slow) write requests.

Speaker Bio:
Dr. Moinuddin Qureshi is a research staff member at IB

M Research. His research interest includes computer architecture, scalabl

e memory system, fault tolerant systems, and analytical modeling of compu

ter systems. His recent research effort is focused on exploiting emerging

technologies for scalable and power-efficient memories and has led to the f

ollowing contributions: Hybrid memory system using PCM (ISCA’09), effici

ent wear leveling for PCM (MICRO’09), and write pausing in PCM (HPCA’10)

. He holds three US patents and has more than a dozen publications in fla

gship architecture conferences. He contributed to the development efficien

t caching algorithms for Power 7 processors. He received his PhD from the U

niversity of Texas at Austin in 2007.