Computer Architecture Seminar Series - Sangyeun Cho/University of Pittsburgh "StimulusCache and MorphCache", ACES 2.402

Contact Name: 
Jenna Whitney
Date: 
Nov 22, 2010 2:00pm - 3:00pm

Type of Talk: Computer Architecture Seminar Series

Speaker

/Affiliation: Sangyeun Cho/University of Pittsburgh

Date/Time: Monday

, November 22, 2010, 2:00 p.m.

Location: ACES 2.402

Host: Lizy

John (ECE), and Kathryn McKinley (CS)

Talk Title: "StimulusCache and

MorphCache"

Talk Abstract:
This talk will focus on our recent multic

ore L2 cache design related research efforts. StimulusCache is motivated by
the fact that future processors can suffer more frequent hard faults. Proc

essor vendors already resort to "core disabling" to combat the low yield pr

oblem caused by hard faults. With core disabling, faulty processor cores a

re taken off-line so that the chip can be salvaged. However, conventional

core disabling ignores the yield disparity between a compute core dominated
by random logic and the associated L2 cache that has a more regular struct

ure. StimulusCache decouples cores and private L2 caches to expose "excess

caches" after core disabling so that they can be beneficially utilized by o

ther healthy cores. MorphCache is designed to efficiently support heterogen

eous workloads (e.g., virtual machines of different users) on many cores.

MorphCache''s novel architecture techniques are its flexible private cache

capacity allocation, distance-aware placement, and efficient broadcasting

. Although these techniques work cooperatively, we found exclusive capacit

y allocation with chain links most important.

Speaker Bio:
Sangyeun

Cho received the BS degree in computer engineering from Seoul National Univ

ersity in 1994 and the PhD degree in computer science from the University o

f Minnesota in 2002. In 1999, he joined the System LSI Division of Samsung
Electronics Co., Giheung, Korea, and contributed to the development of

Samsung''s flagship embedded processor core family CalmRISC(TM). He was a l

ead architect of CalmRISC-32, a 32-bit microprocessor core, and designed

its memory hierarchy including caches, DMA, and stream buffers. Since 200

4, he has been with the Computer Science Department at the University of P

ittsburgh, where he is currently an associate professor. His research inte

rests are in the area of computer architecture and embedded systems with pa

rticular focus on performance, power and reliability aspects of memory and
storage hierarchy design for next-generation multicore systems. Sangyeun i

s the happy father of Seyun (b. December 2009).