Type of Talk: Computer Architecture Seminar Series

Speaker

/Affiliation: Aviral Shrivastava/Arizona State University

Talk Audienc

e: UTCS Faculty, Grads, Undergrads, ECE, and Outside Interested Parties

Date/Time: Wednesday, March 9, 2011, 11:00 a.m.

Location: ACE

S 2.402

Host: Lizy John (ECE) and Kathryn McKinley (CS)

Talk Titl

e: Multi-core Challenge: Missing Memory Virtualization

Talk Abstract:

The multi-core era is irreversibly here. The transition from single-core
to few cores has been relatively smooth. However, the unending need for h

igher performance will bring processors with hundreds and thousands of core

s in the market pretty soon. But what are the implications of this to engin

eering, and software industry in general and computer science in particula

r? How is industry embracing this change? Are we ready?

One of the ch

allenges that we have been working on is the absence of memory virtualizati

on in many-core architectures. Caches were the most important pillar of com

puter architecture in the single-core era. Caches provided the illusion of

a single large unified memory, and kept programming simple and same. Howev

er, caches do not scale well with number of cores, and also consumes a lo

t of power. Therefore to improve the power-efficiency, and enable large nu

mber of cores in a processor, computer architects are in search of alterna

tive memory hierarchies.

Limited Local Memory multi-core architecture

is a scalable memory design in which each core has access to only its small
local memory, and explicit DMA instructions have to be inserted in the pr

ogram to transfer data between memories. The IBM Cell processor, which is

in the Sony Playstation 3 is a popular example of this architecture. The ro

adrunner supercomputer, which broke the peta-scale computation record is o

ne of the most power-efficient super-computers, and is made of IBM Cell pr

ocessors. Such high power-efficiency comes partly at the cost of simplicity
of programming. Programming LLM architecture is not simple, as it require

s application change. Application developers have to be cognizant of the sm

all size of the local memory, and have to insert instructions to perform t

his data transfer between the memories. My talk will summarize our efforts

at automating this memory management.

Speaker Bio:
Aviral Shrivastav

a is Assistant Professor in the School of Computing Informatics and Decisio

n Systems Engineering at the Arizona State University, where he has establ

ished and heads the Compiler and Microarchitecture Labs (CML). He received

his Ph.D. and Masters in Information and Computer Science from University o

f California, Irvine, and bachelors in Computer Science and Engineering f

rom Indian Institute of Technology, Delhi. He is a 2011 NSF CAREER Award R

ecipient and is credited for over $1.5 million of research. His research li

es at the intersection of compilers and architectures of embedded and multi

-core systems, with the goal of improving power, performance, temperatur

e, energy, reliability and robustness. His research is funded by NSF and

several industries including Intel, Nvidia, Microsoft, Raytheon Missile

Systems etc. He serves on organizing and program committees of several prem

ier embedded system conferences, including ISLPED, CODES+ISSS, CASES and
LCTES, and regularly serves on NSF and DOE review panels.

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---------------------------------------------------------------------
The
Computer Architecture Seminar Series is sponsored jointly by the
Departm

ents of Computer Science and Electrical & Computer Engineering
and is sup

ported by a grant from IBM.

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Scalable Yahoo Map of 24th& Speed

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Parking for off-campus visitors: We sugge

st that you park in the San Jacinto
parking garage (formerly PG1) at 24th

& San Jacinto. Parking validation will
be available. Please contact the
host for this seminar or stop by the
refreshment cart to have your parki

ng validated.

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