CS 352H Verilog Info
Before you start...
- We will be using simulation for functional testing and
verification of the verilog code.
- The VCS simulation tool will be used for all testing and
- VCS Documentation
- The full VCS documentation may be found at:
In particular the vcsmx_ug.pdf (VCS User Guide) and the vcsmxqr.pdf (VCS Quick Reference Guide) may be useful.
(note: these links will only work from CS unix machines)
- Verilog HDL is a functional verification and simulation
language for digital systems. There are many sources of information
available on the web for verilog, here are a few highlights:
- There is a free (GPL'ed) verilog mode for
emacs available at verilog.com. It can be extremely useful for
those that use emacs as their primary editor. It has auto
indentation, context sensitive colored highlighting, signal and
command completion as well as pre-processor type functions.
Last modified: 10/13/09
by Don Fussell firstname.lastname@example.org