Speedway Group

Improving Memory System Performance with ML

We're applying deep neural networks and reinforcement learning to design more accurate, timely, high-coverage data prefetchers.

Cross-Layer Automated Accelerator Design

We're building out a pipeline that automatically co-optimizes and generates the hardware and software for dense tensor accelerators.

Rethinking the Hardware-Software Interface for Memory Systems

We're re-examining longstanding principles in ISA design, with a goal of delivering a richer, more flexible load-store interface that delivers finer-grained control of microarchitectural optimization to help mitigate the memory wall.

Q. Duong, A. Jain, and C. Lin. A New Formulation of Neural Data Prefetching. International Symposium on Computer Architecture (ISCA). 2024.

C. Sakhuja, Z. Shi, and C. Lin. Leveraging Domain Information for the Efficient, Automated Design of Deep Learning Accelerators. International Symposium on High-Performance Computer Architectural (HPCA). 2023.

I. Shah, A. Jain, and C. Lin. Effective Mimicry of Belady's MIN Policy. International Symposium on High-Performance Computer Architectural (HPCA). 2022. (Finalist, Best Paper Award)

Z. Shi, A. Jain, K. Swerksy, M. Hashemi, P. Ranganathan, and C. Lin. A Hierarchical Neural Model of Data Prefetching. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 2020. (Micro Top Picks Honorable Mention)

K. Wang, D. Fussell, and C. Lin. A Fast Work-Efficient SSSP Algorithm for GPUs. 26th Annual Symposium on Principles and Practice of Parallel Programming (PPoPP). 2020.

[Full publication list]