TRIPS-Scaling to the Edge of Silicon
TRIPS (The Tera-op, Reliable, Intelligently adaptive Processing System) is a revolutionary new microprocessor architecture being built in the Department of Computer Sciences at The University of Texas at Austin. The team's goal is to produce a scalable architecture that can accelerate industrial, consumer, embedded, and scientific workloads, reaching trillions of calculations per second on a single chip. Connectivity Chart
one trillion
goal-one trillion calculations per second by 2012 fly eye

The TRIPS project is developing a new class of technology-scalable, power efficient, high-performance microprocessor architectures called EDGE (Explicit Data Graph Execution) architectures.

The first EDGE architecture is called TRIPS, and has been designed at the University of Texas at Austin. The TRIPS prototype will offer higher instruction-level concurrency, and thus higher potential performance, than current industrial processors, with no changes to the programming model.

The TRIPS team is currently bringing-up first-silicon in the lab, and is developing the software needed to evaluate this new class of architectures on embedded, streaming, scientific, and desktop workloads. For more information, please send e-mail to

The TRIPS architecture is composed of many copies of a small number of replicated tiles, reducing complexity and improving ease of design. Analogies in nature abound, such as the multiple independent eyes that make up the compound eye of a fly.

The University of Texas at Austin, Department of Computer Sciences
Taylor Hall 2.124, Austin, TX 78712-1188,
512.471.7316, fax 471.8885

University of Texas at Austin, Dept. of Computer Sciences