UT-Austin Computer Architecture Seminar Series

Spring 2000

Location and time:

Presentation schedule:

Date Speaker Title Slides/Papers
Jan. 31 Steven K. Reinhardt
Department of EECS
University of Michigan
Prefetching and Caching Strategies for Modern Memory Systems
Feb. 14
Uri Weiser
Co-Director, Intel Texas Development Center
VLSI: Is it all about integration and performance? Trends and Directions
Feb. 21
Mark Horowitz
Stanford University
What computer architects should know about VLSI scaling Abstract
Feb. 28
Sid Chatterjee
University of North Carolina at Chapel Hill
Fast Tree-Structured Computations and Memory Hierarchies
Mar. 6
Jun Sawada
IBM Austin Research Laboratory
An Introduction to Formal Verification and the FM9801 Project Abstract
Mar. 20
Anand Sivasubramaniam
Department of Computer Science and Engineering
Penn State University
Communication and Scheduling for a Multiprogrammed Cluster
Mar. 27
Dan Dreps
IBM Austin
Wave Pipelined "Elastic" Interface on the POWER4 Chip Abstract
Apr. 3 Trevor Mudge
Department of EECS
University of Michigan
Cool Chips
Apr. 10 Sanjay Jeram Patel
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
Dynamic Optimizations using the rePLay Framework
Apr. 17 Fred Pollack
Director of Microcomputer Research Labs
Intel Corporation
New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies
Apr. 24
Mootaz Elnozahy
IBM Austin Research Lab
Scalability and Performance of a ccNUMA-based Wintel System
May 1 J Strother Moore
Department of Computer Sciences
University of Texas at Austin
Proving Commercial Microprocessors Correct: Recent Results with ACL2

Previous Seminar Series


Comments? Need to schedule a seminar? Contact Yale Patt, Steve Keckler, Doug Burger, or Lizy John.

This seminar series is organized jointly by the Departments of Computer Sciences and Electrical and Computer Engineering at the University of Texas at Austin.

Last modified by dburger@cs.utexas.edu
Thu Jan 6 09:21:19 CDT 2000