TRIPS, Scaling to the Edge of Silicon

TRIPS Tutorial

  • "Design and Implementation of the TRIPS EDGE Architecture," tutorial presented at ISCA-32, Madison, Wi, June 4, 2005. (Version with one slide per page)

  • TRIPS Conference Talks

  • "The Design and Implementation of the TRIPS Prototype Chip," HotChips 17, Palo Alto, CA, August, 2005.

  • "Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures," International Conference on Parallel Architectures and Compilation Techniques (PACT), Antibes Juan-les-Pins, France, October 2004.

  • "TRIPS: Extending the Range of Programmable Processors," Microprocessor Forum, Palo Alto, CA, October, 2003.

  • "Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture," 2003 International Symposium on Computer Architecture (ISCA), , June 2003.

  • "A Wire-Delay Scalable Microprocessor Architecture for High Performance Systems," International Solid-State Circuits Conference (ISSCC), San Fransisco, CA, February 2003.
  • The University of Texas at Austin, Dept. of Computer Sciences