PfHP Blocking for the L1, L2, and L3 caches

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Unit 3.2.5 Blocking for the L1, L2, and L3 caches

The blocking for the various memory layers is captured in the following figure:

Figure 3.2.9. Illustration of the five loops around the micro-kernel. PowerPoint source for figure.

PowerPoint source used in video.

Homework 3.2.5.1.

Using our prior naming convention, which of the implementations

Gemm_IJP_JI_MRxNRKernel.c
Gemm_JPI_JI_MRxNRKernel.c
Gemm_PJI_JI_MRxNRKernel.c

best captures the loop structure illustrated in Figure 3.2.9?

Answer

Gemm_JPI_JI_MRxNRKernel.c