My research interests are in computer architecture, ISA design, memory systems for manycore and multicore architectures, and microarchitectural performance optimization.
I'm also interested in computer science education, particularly in pedagogical and curricular practices to connect more diverse students to computer science and engineering.
I have also been a senior design engineer at ARM Austin (where I designed the unit-level verification environment for the load/store unit and L1 data cache of an out-of-order, cache coherent multicore processor) and a lecturer in both the Department of Computer Science and the Ingram School of Engineering at Texas State University (where I taught computer architecture, digital logic, and CS 2).
In a brief stint as a Ph.D. student at Texas State, I was advised by Dr. Apan Qasem in the Compilers Research Lab (CRL), where I investigated strategies to improve the programmability of heterogeneous systems.
As a masters student, I was a research assistant in Dr. Martin Burtscher's Efficient Computing Laboratory (ECL), where I worked on techniques to efficiently accelerate irregular codes on GPUs. I was fortunate to have my M.S. work supported by a 2011 NSF Graduate Research Fellowship.