Selected Publications

Technology Modeling

• P. Shivakumar, M. Kistler, S.W. Keckler, D.C. Burger, and L. Alvisi. "Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic", 2002 International Conference on Dependable Systems and Networks (DSN), June, 2002. ps pdf

• M.S. Hrishikesh, K. Farkas, N.P. Jouppi, D.C. Burger, S.W. Keckler, and P. Shivakumar. "The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays", Appears in the 29th International Symposium on Computer Architecture (ISCA), May 2002. ps pdf

• M.S. Hrishikesh , D.C. Burger, and S.W. Keckler. "Impact of Technology Scaling on Instruction Execution Throughput", The University of Texas at Austin, Department of Computer Sciences. Technical Report TR-00-06. May 2001. ps pdf
• V. Agarwal, S.W. Keckler, and D.C. Burger. "The Effect of Technology Scaling on Microarchitectural Structures", The University of Texas at Austin, Department of Computer Sciences. Technical Report TR-00-02. May 2001. ps pdf

• S. Gupta, S.W. Keckler, and D.C. Burger. "Technology Independent Area and Delay Estimations for Microprocessor Building Blocks." The University of Texas at Austin, Department of Computer Sciences. Technical Report TR-00-05. February 2001. ps

• V. Agarwal, M.S. Hrishikesh, S.W. Keckler, and D.C. Burger. "Clock Rate Versus IPC: The End of the Road for Conventional Microarchitectures", 27th International Symposium on Computer Architecture (ISCA), June, 2000. ps  pdf

Processor Architectures

• J. Huh, C. Kim, H. Shafi, L. Zhang, D.C. Burger, and S.W. Kekcler. "A NUCA Substrate for Flexible CMP Cache Sharing", The 19th ACM International Conference on Supercomputing (ICS), June, 2005.

• R. Desikan, S. Sethumadhavan, D.C. Burger, and S.W. Keckler. "Scalable Selective Re-Execution for EDGE Architectures" Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2004), October, 2004. ps pdf

• R. Nagarajan, S.K. Kushwaha, D.C. Burger, K.S. McKinley, C. Lin and S.W. Keckler. "Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architecttures" Proceedings of the 13th International Conference on Parallel Architecture and Compilation Techniques (PACT 2004), September, 2004. ps pdf

• K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D.C. Burger, S.W. Keckler, and C.R. Moore. "Exploiting ILP,TLP, and DLP with the Polymorphous TRIPS Architecture" Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), June, 2003. ps pdf

• R. Nagarajan, K. Sankaralingam, D.C. Burger, and S.W. Keckler. "A Design Space Evaluation of Grid Processor Architectures", Proceedings of the 34th Annual International Symposium on Microarchitecture (MICRO), December, 2001. ps pdf

• J. Huh, D.C. Burger, and S.W. Keckler. "Exploring the Design Space of Future CMPs," International Symposium on Parallel Architectures and Compilation Techniques (PACT), September, 2001 ps pdf

• K. Sankaralingam, R. Nagarajan, S.W. Keckler, and D.C. Burger. "A Technology-Scalable Architecture for Fast Clocks and High ILP", 5th Workshop on the Interaction Between Compilers and Computer Architectures (INTERACT-5) at HPCA-7, January, 2001. ps pdf

On-Chip Network Architecture

• B. Grot, S. W. Keckler and O. Mutlu. "Preemptive Virtual Clock: A Flexible, Efficient, and Cost-effective QOS Scheme for Networks-on-a-Chip," Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009. pdf
• B. Grot, J. Hestness, S.W. Keckler, and O. Mutlu. "Express Cube Topologies for On-Chip Interconnects," Proceedings of the 15th International Symposium on High-Performance Computer Architecture (HPCA), February, 2009. pdf
• B. Grot and S.W. Keckler. "Scalable On-Chip Interconnect Topologies," CMP-MSI 2008: 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects, June, 2008. pdf
• P. Gratz, B. Grot, and S.W. Keckler. "Regional Congestion Awareness for Load Balance in Networks-on-Chip," Proceedings of the 14th International Symposium on High-Performance Computer Architecture (HPCA), February, 2008. pdf
• P. Gratz, K. Sankaralingam, H. Hanson, P. Shivakumar, R. McDonald, S.W. Keckler, and D.C. Burger. "Implementation and Evaluation of a Dynamically Routed Processor Operand Network," The 1st ACM/IEEE International Symposium on Networks-on-Chip 2007 (NOCS), May, 2007. pdf
• P. Gratz, C. Kim, R. McDonald, S.W. Keckler, and D.C. Burger. "Implementation and Evaluation of On-Chip Network Architectures", 2006 International Conference on Computer Design (ICCD), October, 2006. pdf

Power

• H. Hanson, M.S. Hrishikesh, V. Agarwal, S.W. Keckler, and D. Burger. "Static Energy Reduction Techniques for Microprocessor Caches," Proceedings of the 2001 International Conference on Computer Design (ICCD), September, 2001. ps pdf

• H. Hanson, M.S. Hrishikesh, V. Agarwal, S.W. Keckler, and D.C. Burger. "Static Energy Reduction Techniques for Microprocessor Caches" IEEE Transactions on VLSI, 2002. pdf
  

• R. Natarajan, H. Hanson, S.W. Keckler, C.R. Moore, and D. Burger. "Microprocessor Pipeline Energy Analysis" IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 282-287, August, 2003. pdf

• M. Valluri, L. John and H. Hanson. "Exploiting Compiler-Generated Schedules for Energy Savings in High-Performance Processors" Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), Seoul, Korea, 2003. pdf

• H. Hanson, S.W. Keckler and D. Burger. "Coordinated Power, Energy, and Temperature Management for High-Performance Microprocessors" Proceedings of the Austin Center for Advanced Studies [IBM] Conference, February, 2004. pdf

• H. Hanson, S.W. Keckler. "Coordinated Management: Power, Performance, Energy, and Temperature," Proceedings of the Austin Center for Advanced Studies [IBM] Conference, February, 2005. pdf

• H. Hanson, S.W. Keckler. "Power and Performance Optimization: A Case Study with the Pentium M Processor," Proceedings of the Austin Center for Advanced Studies [IBM] Conference, February, 2006. pdf

• M. Valluri, L. John and H. Hanson. "Hybrid-Scheduling: A Technique to Exploit Static Schedules for Reduced Energy Consumption in High-Performance Processors," IEEE Transactions on VLSI, September 2006.

• H. Hanson, S.W. Keckler, K. Rajamani, S. Ghiasi, F. Rawson, J. Rubio. "Power, Performance, and Thermal Management for High-Performance Systems" 3rd Workshop on High-Performance, Power-Aware Computing (HPPAC 2007), held in conjunction with 21st Annual International Parallel & Distributed Processing Symposium (IPDPS 2007), March, 2007. pdf

• H. Hanson, S.W. Keckler, S. Ghiasi, K. Rajamani, F. Rawson, J. Rubio. "Thermal Response to DVFS: Analysis with an Intel Pentium M" To appear in the International Symposium on Low-Power Electronics (ISLPED), August, 2007. pdf

Applications

• K. Agaram, S.W. Keckler, and D.C. Burger. Last updated Sat Nov 9 16:20:59 CST 2002 "A Characterization of Speech Recognition on Modern Computer Systems." 4th Annual IEEE Workshop on Workload Characterization, December 2001. pdf

• K.K. Agaram, S.W. Keckler, and D.C. Burger. "Characterizing the SPHINX Speech Recognition System." The University of Texas at Austin, Department of Computer Sciences. Technical Report TR-00-33. January 2001. ps

Simulation

• Doug Burger, Alain Kagi, and M.S. Hrishikesh. "Memory Hierarchy Extensions to the Simplescalar Tool Set", The University of Texas at Austin, Department of Computer Sciences. Technical Report TR-99-25. ps
• R. Desikan, D.C. Burger, and S.W. Keckler. "Measuring Experimental Error in Microprocessor Simulation.", 28th International Symposium on Computer Architecture (ISCA), pp. 266-277, July, 2001. ps pdf

• K. Sankaralingam, R. Nagarajan, S.W. Keckler, and D.C. Burger. "SimpleScalar Simulation of the PowerPC Instruction Set Architecture." The University of Texas at Austin, Department of Computer Sciences. Technical Report TR-00-04. February 2001. ps

• R. Desikan, D.C. Burger, S.W. Keckler, and Todd Austin. "Sim-alpha: a Validated, Execution-Driven Alpha 21264 Simulator.", The University of Texas at Austin, Department of Computer Sciences. Technical Report TR-01-23. ps

Emerging Technologies

• R. Desikan, S.W. Keckler, and D.C. Burger. "Assessment of MRAM Technology Characteristics and Architectures", The University of Texas at Austin, Department of Computer Sciences. Technical Report TR-01-36. pdf

• R. Desikan, C.R. Lefurgy, S.W. Keckler, and D.C. Burger. "On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories", The University of Texas at Austin, Department of Computer Sciences. Technical Report TR-02-47. ps pdf

Memory Systems (Burger)

• D.C. Burger and J.R. Goodman. "Why Future Architectures will be Memory-Centric,"
  Innovative Architecture for Future Generation High_Performance Processors and Systems, IEEE Computer Society Press, p. 92, 1998.

• D.C. Burger, S. Kaxiras, and J.R. Goodman. "DataScalar Architectures,"
  24th International Symposium on Computer Architecture (ISCA), pp. 338-349, June, 1997.

• A. Kägi, D.C. Burger, and J.R. Goodman. "Efficient Synchronization: Let Them Eat QOLB,"
  24th International Symposium on Computer Architecture (ISCA), pp. 170-180, June, 1997.

• D.C. Burger. "System-Level Implications of Processor/Memory Integration,"
  Workshop on Mixing Logic and DRAM, at the 24th International Symposium on Computer Architecture (ISCA), June, 1997.

• D.C. Burger and T.M. Austin. "The SimpleScalar Tool Set, Version 2.0,"
  Computer Architecture News, 25 (3), pp. 13-25, June, 1997.

• D.C. Burger, J.R. Goodman, and A. Kägi. "Memory Bandwidth Limitations of Future Microprocessors,"
  23rd International Symposium on Computer Architecture (ISCA), pp. 78-89, May, 1996.

M-Machine (Keckler)

• S.W. Keckler, A. Chang, W.S. Lee, S. Chatterjee, and W.J. Dally, "Concurrent Event Handling Through Multithreading", IEEE Transactions on Computers, 48:9, September, 1999, pp 903-916.

• W.S. Lee, W.J. Dally, S.W. Keckler, N.P. Carter, and A. Chang, "Efficient Protected Message Interface in the MIT M-Machine", IEEE Computer, pp. 69-75, November 1998.

• A. Chang, W.J. Dally, S.W. Keckler, N.P. Carter, and W.S. Lee. "The Effects of Explicitly Parallel Mechanisms on the Multi-ALU Processor Cluster Pipeline", International Conference on Computer Design (ICCD), pp. 474-481, October 1998.

• S.W. Keckler, W.J. Dally, D. Maskit, N.P. Carter, A. Chang, and W.S Lee. "Exploiting Fine-Grain Thread Level Parallelism on the MIT Multi-ALU Processor", 25th Annual International Symposium on Computer Architecture (ISCA), pp. 306-317, July 1998.

• S.W. Keckler, W.J. Dally, A. Chang, N.P. Carter, and W.S Lee. "The MIT Multi-ALU Processor", Proceedings of Hot Chips IX, pp. 1-8, August 1997.

• M. Fillo, S.W. Keckler, W.J. Dally, N.P. Carter, A. Chang, Y. Gurevich, and W.S Lee. "The M-Machine Multicomputer", Proceedings of the 28th Annual International Symposium on Microarchitecture (MICRO), pp. 146-156, December 1995.

• N.P. Carter, S.W. Keckler, and W.J. Dally, "Hardware Support for Fast Capability-based Addressing", International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VI), pp. 319-327, October 1994.

• S.W. Keckler, and W.J. Dally, "Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism", International Symposium on Computer Architecture (ISCA), pp. 202-213, May 1992.

Performance Evaluations

• K.B. Bush, M. Gebhart, D. Burger, S.W. Keckler, A Characterization of High Performance DSP Kernels on the TRIPS Architecture", Department of Computer Sciences, University of Texas, TR-06-62, November, 2006,