Işıl Dillig
Professor
Research
Research Interests:
- Program Analysis and Verification
- Program Synthesis
- Automated Logical Reasoning
Current Research:
Prof. Dillig's main research interests are program analysis/verification, program synthesis, and automated logical reasoning. She is interested in developing tools and novel techniques to make software systems more secure and reliable. In particular, her research focuses on automatically proving the absence of certain classes of errors and security vulnerabilities in software. She is also interested in techniques for automatically synthesizing programs from formal or informal specifications.
Select Publications
Yu Feng, Ruben Martins, Osbert Bastani, Isil Dillig. 2018. Program Synthesis using Conflict-Driven Learning. PLDI.
Yu Feng, Xinyu Wang, Isil Dillig, Calvin Lin. 2015. EXPLORER : Query- and Demand-Driven Exploration of Interprocedural Control Flow Properties. OOPSLA.
John Feser, Swarat Chaudhuri, Isil Dillig. 2015. Synthesizing Data Structure Transformations from Input-Output Examples. PLDI.
Oswaldo Olivo, Isil Dillig, Calvin Lin. 2015. Static Detection of Asymptotic Performance Bugs in Collection Traversals. PLDI.
Yu Feng, Saswat Anand, Isil Dillig, Alex Aiken. 2014. Apposcopy: Semantics-Based Detection of Android Malware Through Static Analysis. FSE.
Awards & Honors
2018 -
PLDI Distinguished Paper Award
2017 -
OOPSLA Distinguished Paper Award
2017 -
ETAPS Best Paper Award
2015 -
Sloan Fellow
2015 -
NSF CAREER Award
2012 -
Distinguished Reviewer Award, OOPSLA
2010 -
Stanford Graduate Fellowship
2007 -
Forbes School of Engineering Fellowship
2006 -
Wegbreit Award
2006 -
Firestone Meda